1. Field of the Invention
The present invention relates to an asymmetric multiprocessor for controlling a dedicated signal processing hardware, a DSP (Digital Signal Processor) and a reconfigurable processor in a microprocessor and a media processor.
2. Description of the Related Art
Processors provided to mobile telephones of the recent years provided with Internet access function are configured with high-performance media processor engines (combinations of a DSP or a CPU and a hardware accelerator) that are capable of performing Java (registered trademark) program processing, web connection control, audio processing or graphics processing, image processing such as MPEG (Moving Picture Experts Group), digital TV, games, and the like in addition to speech processing and baseband processing. For such multimedia processors, a distributed processing multiprocessor is expected as a means of enhancing the efficiency of software development, reducing the surface area to be implemented on LSI (Large Scale Integration) and reducing operating currents.
In a conventional asymmetric multiprocessor, a plurality of processors are provided, and the processors are different from each other in any or all of performance (such as an operating frequency), command set and architecture (such as a bit width or a memory size, a cache size and the number of stages of pipelines).
There are also cases, for example, where the processing shares (role shares) of the CPUs are decided in advance in an asymmetric multiprocessor provided with a plurality of CPUs. In this case, the CPUs are configured to make a slave connection with a dedicated signal processing hardware circuit (hardware accelerator) or a DSP according to the role shares (see Japanese Patent Application Laid-open No. 2004-252900, for example).
FIG. 1 shows a configuration of the conventional asymmetric multiprocessor.
In FIG. 1, asymmetric multiprocessor system 10 is configured with CPU cores 11a through 11c (CPU #1 through #3), cache memory (hereinafter referred to as caches) 12a through 12c ($1 through $3), ROM 13, RAM 14, CPU core 11a (CPU #1) slave/hardware (hereinafter abbreviated as HW as appropriate) accelerator sections 15a through 15c (HW #1a through #1c), CPU core 11b (CPU #2) slave/hardware accelerator sections 16a and 16b (HW #2a and #2b), CPU core 11c (CPU #3) slave/hardware accelerator sections 17a and 17b (HW #3a and #3b), and other components. CPU cores 11a through 11c (CPU #1 through #3) are each connected to ROM 13 and RAM 14 via common bus 18 and cache memory 12a through 12c ($1 through $3). CPU core 11a (CPU #1) and slave/hardware accelerator sections 15a through 15c (HW #1a through #1c) are connected by local bus 19; CPU core 11b (CPU #2) and slave/hardware accelerator sections 16a and 16b (HW #2a and #2b) are connected by local bus 20; and CPU core 11c (CPU #3) and slave/hardware accelerator sections 17a and 17b (HW #3a and #3b) are connected by local bus 21.
Portions of the above-described slave/hardware accelerator sections 15a through 15c, 16a, 16b, 17a and 17b are configured, for example, with DSPs and functional blocks such as video signal processing blocks, audio signal processing blocks and control signal processing blocks.
According to the technique of dividing the processing executed on a software program among the above-described different processor architectures, it is possible to obtain an effect of suppressing hardware resource compared to the case where the processing is performed in a single processor, and an effect of reducing power consumption by reducing clock frequencies of the processors as a result of dividing the processing shares.
However, in such a conventional asymmetric multiprocessor, a plurality of unit jobs for which the amount of jobs is predictable are divided among a plurality of processors for each unit job, and therefore the effect of reducing power consumption is often small depending on the prediction algorithm or the prediction system.
In the asymmetric multiprocessor disclosed in Japanese Patent Application Laid-open No. 2004-252900, the processing contents of the CPUs are often fixed to some extent when the overall configuration (processor architecture design) of the multiprocessor is determined. Along with this, like the asymmetric multiprocessor shown in FIG. 1, slave/hardware accelerator sections 15a through 15c, 16a, 16b, 17a and 17b for supporting acceleration of the processing of the CPUs are made a dedicated connection with CPU cores 11a through 11c via local buses 19 through 21, respectively. Therefore, even when the content of the processed program changes and the processing amount increases, the processing amount cannot be readily shared (program task sharing) among the plurality of CPU cores 11a through 11c, and therefore there is only a small degree of freedom in the load distribution.
In both of the former asymmetric multiprocessor and the latter asymmetric processor disclosed in Japanese Patent Application Laid-open No. 2004-252900, and, even in the asymmetric multiprocessor having both elements, a plurality of CPUs, hardware accelerators, DSPs, or the like operate simultaneously, and therefore, there is a problem of an increase in power consumption within the LSI.
Further, there are methods for achieving low power consumption by varying (or reducing) the operating frequency by performing distributed processing, and varying (or reducing) the operating frequency and the power supply voltage.
However, the design of a clock tree that assumes distributed processing becomes complicated, and the IR drop (voltage drop or voltage fluctuation) of the power supply voltage in the case of operation at the maximum operating frequency, or the dynamic power supply noise increases, and malfunction of the LSI becomes a problem.